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VILLASfpga interconnects simulators and devices under test (DUT) for hardware-in-the loop simulation using hard real-time capable interfaces. VILLASfpga can guarantee fixed latencies in the nanosecond range. VILLASfpga is using Xilinx' FPGA evaluation boards to interfaces such devices to each other and to the Linux host system via PCIexpress.

It implements intellectual property (IP) cores for connecting:

VILLASfpga can be configured to connect these interfaces in an arbitrary fashion without the need of generating a new bitstream. This is realized by using a software configurable switch in the FPGA fabric.

VILLASfpga is based on ARM's AXI-4 Stream interfaces and therefore relying on Xilinx's Vivado toolchain. This limits the the range of supported FPGA families to Virtex 6, 7 and the newer Ultrascale devices. Bitstreams for the Xilinx VC707 FPGA evaluation board are available upon request.


The VILLASfpga project is splitted into two Git repositories:


export PKG_CONFIG_PATH=/usr/local/lib/pkgconfig
git clone
pushd VILLASfpga
git submodule update --init --recursive
mkdir -p thirdparty/libxil/build
pushd thirdparty/libxil/build
cmake ..
sudo make -j$(nproc) install
mkdir build
cmake ..
sudo make -j$(nproc) install

Running loopback test

Check that system is booted with IOMMU support:

find /sys | grep dmar

If not add intel_iommu=on to the kernel commandline and reboot.

sudo modprobe vfio
sudo modprobe vfio_pci

sudo VILLASfpga/build/src/villas-fpga-pipe