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Configuration

caution

This section is outdated!

VILLASfpga is configured using the standard VILLASnode configuration file. Unlike other node types, the VILLASfpga node type requires settings in two places:

FPGA Card​

This section is a group (similar to nodes) that allows the user to use multiple FPGA devices simultaneously. Similar to nodes, each FPGA has its own name:

id (string: "vendor:product")​

A string containing the vendor and product ID of the FPGA card, as shown by lspci.

slot (string)​

The slot in which the FPGA card is located, as shown by lspci.

intc (integer: base address)​

The AXI4-Lite base address used to access the interrupt controller's registers.

reset (integer: base address)​

The AXI4-Lite base address used to access the reset controller's registers.

do_reset (boolean)​

Should VILLASnode perform a reset of the FPGA board on startup?

paths (array of groups)​

A list of connections within the FPGA fabric that should be configured. This is analogous to the paths configuration section of VILLASnode.

Example​

fpgas = {
	vc707 = {
		/* Card identification */
		id = "10ee:7022";
		slot = "01:00.0";

		intc  = 0x5000;
		reset = 0x2000;
		do_reset = true;

		/* Configure switch_0 */
		paths = (
			{ in = "dma_0",  out = "rtds_0" },
			{ in = "rtds_0", out = "dma_0" }
		)
	}
}

FPGA IP core​

Each FPGA IP core requires at least the following setting: Depending on the VLNV of each IP core, you can configure additional settings.

vlnv (string: "vendor:library:name:version:)​

A VLNV identifier to properly identify the version and type of this IP core.

baseaddr (integer: baseaddr)​

The base address for register access.

port (integer)​

The port number of the switch to which this IP core is connected.

Example​

fpgas = {
	vc707 = {
		ips = {
			switch_0 = {
				vlnv = "xilinx.com:ip:axis_interconnect:2.1"
				baseaddr = 0x0000;
				numports = 3;
			},
			rtds_0 = {
				vlnv = "acs.eonerc.rwth-aachen.de:user:rtds_axis:1.0"
				baseaddr = 0x3000;
				port = 0;
			},
			dma_0 = {
				vlnv = "xilinx.com:ip:axi_dma:7.1";
				baseaddr = 0x1000;
				port = 2;
				irq = 0
			}
		}
	}
}